<?xml version="1.1" encoding="utf-8"?>
<article xsi:noNamespaceSchemaLocation="http://jats.nlm.nih.gov/publishing/1.1/xsd/JATS-journalpublishing1-mathml3.xsd" dtd-version="1.1" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"><front><journal-meta><journal-id journal-id-type="publisher-id">SSR</journal-id><journal-title-group><journal-title>Scientific and Social Research</journal-title></journal-title-group><issn>2661-4332</issn><eissn>2981-9946</eissn><publisher><publisher-name>Bio-Byword Scientific Publishing Pty. Ltd.</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.26689/ssr.v7i3.10014</article-id><article-categories><subj-group subj-group-type="heading"><subject>Article</subject></subj-group></article-categories><title>High-Speed Bandwidth Acquisition System Based on Intermediate Frequency Signal Processing</title><url>https://artdesignp.com/journal/SSR/7/3/10.26689/ssr.v7i3.10014</url><author>YinZiming,WeiYunyu,WangKuo</author><pub-date pub-type="publication-year"><year>2025</year></pub-date><volume>7</volume><issue>3</issue><history><date date-type="pub"><published-time>2025-04-03</published-time></date></history><abstract>In the high-speed bandwidth acquisition and playback system, due to the current hardware conditions, it is impossible to directly sample the signal at the RF end. Therefore, first complete the down-conversion in the RF module, reduce the signal to the intermediate frequency, and then realize the digitization of the intermediate frequency signal. In response to this problem, a field programmable logic array chip (FPGA) and AD9680 were selected to process the intermediate frequency signal. Use AD9680 to collect the mid-band pass signal with a center frequency of 750 MHz and a bandwidth of 400 MHz as a signal source for test verification, and then pass through a parallel multiphase digital down-conversion module to achieve spectrum shifting. It is verified by testing that the design can normally process the intermediate frequency signal, and the out-of-band suppression reaches 60 dB, which meets the design requirements, has high stability, and has high application value in engineering applications.</abstract><keywords/></article-meta></front><body/><back><ref-list><ref id="B1" content-type="article"><label>1</label><element-citation publication-type="journal"><p>He S, 2020, Research on Key Technologies of Broadband Signal High-speed Acquisition and Transmission System, thesis, North University of China.</p><pub-id pub-id-type="doi"/></element-citation></ref><ref id="B2" content-type="article"><label>2</label><element-citation publication-type="journal"><p>Li ZJ, 2019, Development of PXIe Intermediate Frequency Digitizer, thesis, Harbin Institute of Technology.</p><pub-id pub-id-type="doi"/></element-citation></ref><ref id="B3" content-type="article"><label>3</label><element-citation publication-type="journal"><p>Zhao YL, 2008, Design and Implementation of Signal Acquisition and Processing System based on FPGA, thesis, Nanjing University of Science and Technology.</p><pub-id pub-id-type="doi"/></element-citation></ref><ref id="B4" content-type="article"><label>4</label><element-citation publication-type="journal"><p>Peng DL, Wang X, Chen XH, et al., 2013, Hardware Circuit Design of High-speed Data Acquisition System based on Band-pass Sampling Theorem. Instrumentation Technology and Sensors, 2013(5): 72–74.</p><pub-id pub-id-type="doi"/></element-citation></ref><ref id="B5" content-type="article"><label>5</label><element-citation publication-type="journal"><p>Wu NX, 2020, Research on FPGA-based High-speed and High-precision ADC/DAC Data Deep Storage and Digital Frequency Conversion System, thesis, University of Chinese Academy of Sciences (School of Artificial Intelligence, Chinese Academy of Sciences).</p><pub-id pub-id-type="doi"/></element-citation></ref></ref-list></back></article>
